Recently, semiconductor devices such as a LSI or the like have been required to have higher density in order to meet requirements for reducing the mounting space or for improving the processing rate. As an example of a technology that achieves the high density, there has been known a multilayer wiring technology of manufacturing a multilayer substrate, such as a three-dimensional LSI or the like, by stacking multiple wiring substrates.
According to the multilayer wiring technology, a TSV (Through Silicon Via), which penetrates the wiring substrates and in which a conductive material such as copper (Cu) is buried, is typically formed in the wiring substrate in order to obtain electrical connection between the wiring substrates. As an example of a technology for forming the TSV in which a conductive material is buried, there has been known an electroless plating method.
In case of forming a metal film by electroless plating, it is required to improve adhesivity between a base and the metal layer. For the purpose, conventionally, a self-assembled monolayer (SAM) is formed on the base by using a coupling agent such as a silane coupling agent or a titanium coupling agent, and a catalytic metal such as palladium particles is provided on the base with the self-assembled monolayer therebetween. For example, as described in Patent Document 1, by supplying a catalytic particle solution containing palladium nanoparticles coated with a dispersing agent such as PVP (PolyvinylPyrrolidone), the catalytic metal can be adsorbed onto the self-assembled monolayer.
However, adhesiveness of the palladium nanoparticles is not sufficiently high, so that the palladium nanoparticles may be separated from the base during a cleaning process which is performed prior to a subsequent barrier layer forming process of forming a barrier layer by electroless plating. As a result, a sound barrier layer may not be formed. If the soundness of the barrier layer is low, the soundness of layers formed on the barrier layer, such as a seed layer and a copper plating layer forming a wiring, may also be weakened.
Patent Document 1: Japanese Patent Laid-open Publication No. 2013-067856.